A 10 Gb/s Equalizer in 0.18μm CMOS Technology for High-speed SerDes
نویسندگان
چکیده
A 10 Gb/s equalizer consisting of analog equalizer and two-tap halfrate decision feedback equalizer (DFE) in a 0.18μm CMOS has been designer. By employing capacitive degeneration and inductive peaking techniques, the analog equalizer achieves large boosting. The pipelined half-rate architecture is used to improve the transmitted data rate in DFE with a small increase in area. Measurement results show that the distorted signal is well recovered by this equalizer and consumes 27 mW with the supply voltage of 1.8-V. The overall chip area including pads is 0.6×0.7 mm2. Keyword: analog equalizer; decision feedback equalizer (DFE); capacitive degeneration; inductive peaking; current mode logic (CML)
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